The subject matter disclosed herein relates to diodes and, more specifically, to active area designs for charge-balanced diodes.
For semiconductor power devices, charge-balanced (also referred to as super-junction) designs offer several advantages. For example, charge-balanced devices demonstrate reduced drift layer resistance and thus reduced conduction losses per unit area relative to traditional unipolar device designs. In silicon (Si) charge-balanced devices, an active area may be formed by implanting or diffusing a number of vertical pillars of a first dopant type (e.g., p-type) into a Si device layer of a second dopant type (e.g., n-type). The vertical pillars of these Si charge-balanced devices extend through the thickness (e.g., tens of micrometers) of the Si epitaxial device layer, which can be achieved using existing Si epitaxy, implantation and/or diffusion methods.
However, in silicon carbide (SiC), dopants have significantly lower diffusion coefficient/implantation range than in Si. As a result, when a feature (e.g., a vertical charge-balance region) is formed into a SiC epitaxial layer using an implantation energy that is typical of Si processing, the dopants are unable to penetrate into the SiC layer as deep as they would into the Si layer. For example, typical commercial ion implantation systems for Si device fabrication utilize dopant implantation energies up to about 380 keV. Such implantation energies only enable dopant implantation to a maximum depth between approximately 0.5 μm and approximately 1 μm into the surface of a SiC epitaxial layer.